This invention relates to semiconductor devices in general and more particularly to semiconductor device isolation by wafer to wafer bonding.
It is known that two flat, smooth, hydrophilic surfaces can be bonded (or "contacted") at room temperature without the use of external forces. The bonded materials may be metallic, semiconducting, or insulating in nature. The contacting forces are believed to be caused by attraction between hydroxyl groups (--OH) and possibly some water molecules adsorbed on the two mating surfaces. This attraction causes the spontaneous formation of hydrogen bonds across the gap between two wafers. The spontaneity in the initiation of the contacting occurs only between exceptionally flat, smooth, and clean surfaces. Once initiated, this bonding process can spread in a form of "contacting wave" throughout the entire area between two silicon wafers with speeds of several cm/sec. The hydroxyl groups are usually attached to the surface through the reaction of a clean surface oxide with the moisture from the air or atomized water source.
The bonding of silicon wafers is one of the most promising techniques for the formation of silicon on insulator (SOI) wafers. Specifically, wafer bonding makes it possible to bury oxide and implantation layers within the bulk of a monocrystalline silicon wafer, and for this reason it has been utilized as a highly flexible and low cost alternative for SOI and epitaxial growth.
Currently, two basic approaches are employed in the fabrication of SOI wafers by wafer bonding, these differing primarily in the method of thinning the device (or seed) wafer, which is bonded to the substrate (or handle) wafer, to an appropriate device film thickness. In the first technique, a dielectric layer (such as SiO.sub.2) is formed on the handle wafer. The polished face of the device wafer is contacted with that of the handle wafer in ambient temperature and atmosphere. A full strength seal is obtained by bonding the contacted wafers at a temperature of at least 1150.degree. C. for at least one hour or greater. The bonded pair are precision lapped and polished from the device wafer side to the desired thickness of the silicon device layer. The resulting silicon film thickness uniformity is limited by the thickness uniformity of the handle wafer, which is on the order of 0.3 .mu.m.sup.2.
The second technique involves an etch back of the device wafer. A highly selective etch stop is formed by implantation, epitaxy or diffusion in the device wafer prior to bonding. As in the first technique, the polished face of the device wafer is contacted with that of the handle wafer in ambient temperature and atmosphere and the pair are bonded at 1150.degree. C. for an hour. The bonded wafers are subjected to an etching process from the device wafer side in which almost all of the device wafer is removed, thereby leaving a thin device layer which is subsequently patterned and etched using conventional photolithography.
A principal disadvantage of the above techniques, however, is the difficulty in uniform sealing at the interface of the mated wafers due to the presence of bubbles and voids. Interface bubbles are caused by dust particles and insufficient wafer flatness. While the latter problem can be avoided by appropriate wafer specification, it is extremely difficult to obtain totally dust-free wafer surfaces prior to the bonding procedure. In an article appearing in Vol. 27, No. 12 of the Japanese Journal of Applied Physics (1988), R Stengl et al. reported that even for wafers mated in a class 1 cleanroom, about 70% of the wafers contained one or more bubbles due to dust particles less than 1 micron in diameter.
An additional disadvantage of such techniques is the interval of time required to obtain a high reliability, full strength seal between the mating surfaces. As indicated above, sealing by prior art techniques requires at least one hour at 1150.degree. C. or greater to obtain a full strength seal.
Yet another disadvantage of such techniques is that the implantation or diffusion layer must be etched to form the desired circuit pattern after the etch back of the non-bonded surface of the device wafer. As a result, fine line patterns, which are desired in certain pressure transducer applications or very large scale integration applications, can not be obtained due to limitations in the etching process.
Accordingly, it is a principal object of the present invention to provide a method of forming silicon on insulator (SOI) wafers by fusion bonding which avoids the aforementioned problems associated with the prior art.